This invention relates generally to semiconductor product fabrication processes, and more particularly the invention relates to devices and methods for monitoring deleterious effects in semiconductor wafers due to charge induced damage during fabrication of integrated circuits and semiconductor devices.
It is known that semiconductor processes such as ion implantation, plasma etching, and other charged beam processing may cause damage in semiconductor wafers and the devices and circuits fabrication therein. To assess the damage-generating tendency of such processes, and to determine safe integrated circuit layout guidelines, the semiconductor industry has used polysilicon capacitors with varying gate oxide-field oxide ratios, edge-area ratios, and the like to statistically assess the manner and extent to which these parameters influence the degree of damage, and to develop or select more benign process options. However, due to the indirect nature of this monitoring procedure which relies on compiling frequency of oxide breakdown voltage or charge to breakdown statistics, the results have frequently been inconclusive and confusing.
More recently, the Center for Integrated Systems at Stanford University has developed a monitor for use during plasma etching and high current arsenic implants, as described by Lukaszek et al., "CHARM, a New Wafer Surface Charge Monitor," Tech Con '90, San Jose. The charge monitor device uses electrically erasable PROM transistors as shown in FIG. 1 whose control gates are connected to aluminum charge collection electrodes located on thick oxide. Electrostatic charge deposited on the collection electrodes gives rise to a potential proportional to the amount of deposited charge and the collection electrode to substrate oxide thickness. This potential programs the EEPROM memory transistors by altering their threshold voltages in proportion to the potential on the charge collection electrodes. Therefore, the monitor is a polarity-sensitive peak voltage detector with memory. Its threshold voltage shift versus control gate potential, shown in curve A of FIG. 2, is determined during wafer probe by repeated application of external voltages to the charge collection electrodes.
Two undesirable characteristics may be observed in curve A: as manufactured, the EEPROM transistor does not respond to applied voltages between -10 volts and +10 volts, and the threshold voltage shift saturates for applied voltages lower than -25 volts or greater than +30 volts. The absence of response between -10 and +10 volts indicates that the applied potential is insufficient to cause electron tunneling through the thin tunnel oxide, while the saturation is due to reverse tunneling across the tunnel oxide when the floating gate potential is sufficiently low (or high) and the external programming voltage is removed. The lack of response between -10 volts and +10 volts can be circumvented by preprogramming the monitor transistors to their saturated threshold voltage state, where the transistors will respond to the slightest potential of the opposite polarity, as indicated in curves (b) and (c) of FIG. 2. Thus, the entire range of surface potential between -25 volts and +30 volts can be monitored by this device.
Early experimental results with this device indicate that the wafer charging during high current arsenic implants was best modeled by a voltage source whose polarity was negative. However, these bipolar, fast response charge monitoring devices leave unresolved the possibility of earlier occurrence of possibly detrimental positive transients whose signature was erased by subsequent negative transients. The use of unspecialized EEPROM to monitor charging effects during high current ion implants and plasma etching is inappropriate due to their bipolar sensitivity and convolved electrostatic and UV effects. Further, the structures described above appear to be inappropriate due to their bipolar response and excessively high sensitivity.
Ideally, a monitor is needed which gives a direct measure of the driving force behind the damage.
The present invention is directed to an improved charge monitoring device which overcomes limitations of the earlier EEPROM charge monitoring devices.